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L9929
SPI CONTROLLED H-BRIDGE
PRELIMINARY DATA
1

Features
OPERATING SUPPLY VOLTAGE 5V TO 28V TYPICAL RDSon = 150 m FOR EACH OUTPUT TRANSISTOR (AT 25C) CONTINOUS DC LOAD CURRENT 5A (Tcase < 100 C) OUTPUT CURRENT LIMITATION AT TYP. 8.6A SHORT CIRCUIT SHUT DOWN FOR OUTPUT CURRENTS OVER TYP. 10.6A LOGIC- INPUTS TTL/CMOS-COMPATIBLE OPERATING-FREQUENCY UP TO 30 kHz OVER TEMPERATURE PROTECTION SHORT CIRCUIT PROTECTION UNDERVOLTAGE DISABLE FUNCTION DIAGNOSTIC BY SPI OR STATUS-FLAG (CONFIGURABLE) ENABLE AND DISABLE INPUT SO20 POWER PACKAGE
Figure 1. Package
PowerSO20
PowerSSO24

Table 1. Order Codes
Part Number L9929 L9929XP Package PowerSO20 PowerSSO24

The H-Bridge is protected against over temperature and short circuits and has an under voltage lockout for all the supply voltages "VS" (Main DC power supply). All malfunctions cause the output stages to go tristate. The H-Bridge contains integrated free-wheel diodes. In case of free-wheeling condition, the low side transistor is switched on in parallel of its diode to reduce the current injected into the substrate. Switching in parallel is only allowed, if the voltage level of the according output-stage is below the ground-level. In this case it must be ensured, that the upper transistor is switched off.

2
Description
The L9929 is an SPI controlled H-Bridge, designed for the control of DC and stepper motors in safety critical applications and under extreme environmental conditions. Figure 2. Block Diagram
VS UNDERVOLTAGE VS INTERNAL 5V SUPPLY
IN1 IN2 GATE CONTROL 1 GATE CONTROL 2 LOGIC DMS SF/SCK SS SI SO MAXIMUM CURRENT LIMITATION GND
D01AT470A
OVERCURRENT HIGH-SIDE OUT1
DI EN
OUT2 OVER TEMPERATURE OVERCURRENT LOW-SIDE
May 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 2 1/23
L9929
Table 2. Pin Function PowerS020
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME GND SCK/SF IN1 VS VS OU1 OU1 SO SI GND GND DMS EN OU2 OU2 VS SS DI IN2 GND Ground SPI-Clock/Status-flag Input 1 Supply voltage Supply voltage Output 1 Output 1 serial out serial in Ground Ground Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface) Enable Output 2 Output 2 Supply voltage Slave select Disable Input 2 Ground Description
Figure 3. Pin Connection (Top view)
GND SCK IN1 VS VS OU1 OU1 SO SI GND
1 2 3 4 5 6 7 8 9 10
D01AT471
20 19 18 17 16 15 14 13 12 11
GND IN2 DI SS VS OU2 OU2 EN DMS GND
2/23
L9929
Table 3. Pin Function PowerSS024
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME GND SCK/SF IN1 N.C. VS VS OUT1 OUT1 SO SI GND GND GND GND DMS EN OUT2 OUT2 VS SS DI IN2 N.C. GND Ground SPI-Clock Input 1 Not Connected Supply voltage Supply voltage Output 1 Output 1 Serial Out Serial In Ground Ground Ground Ground Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface) Enable Output 2 Output 2 Supply voltage Slave select Disable Input 2 Not Connected Ground Description
Figure 4. Pin Connection (Top view)
GND SCK INPUT 1 N.C. VS VS OUT 1 OUT 1 SO SI GND GND
1 2 3 4 5 6 7 8 9 10 11 12
D05AT527
24 23 22 21 20 19 18 17 16 15 14 13
GND NC INPUT 2 DISABLE SS VS OUT 2 OUT 2 ENABLE DMS GND GND
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L9929
Table 4. Absolute Maximum Ratings The integrated circuit must not be destroyed by use at the limit values. Each limit value can be used, as long as no other limit is violated. Voltage reference point: All values are, if not otherwise stated, relative to ground. Direction of current flow: Current flow into a pin is positive. Rise-, fall- and delaytimes: If not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps.
Symbol VS Parameter Supply voltage Test Condition static destruction proof dynamic destruction proof t <0.5s (single pulse, Tj < 85C) VLI VLO Logic inputs IN1, IN2, DI, EN, SS, SI, SCK,DMS Logic outputs SF, SO Min. -1 -2 -0.5 -0.5 Typ. Max. 40 40 7 7 Unit V V V V
Table 5. Thermal Data
Symbol Tj Tstg Tamb Parameter Junction temperature dynamic t < 1 s Storage temperature Ambient temperature -55 -40 Test Condition Min. -40 Typ. Max. +150 +175 +125 +125 3 160 150 175 165 190 180 Unit C C C C C/W C C
Rth j-case Thermal resistance junction to case (*) Tj_sd Tj_reg Thermal Shutdown Junction Temperature Threshold Start of Temperature dependent Current Regulation
(*) Guaranteed by design and package characterization.
Table 6. Electrical Characteristcs ( Tj = -40 to +150C; VS = 5 to 28V)
Symbol POWER SUPPLY VS Supply Voltage Undervoltage Shutdown Switch OFF voltage Switch ON voltage Hysteresis VDMS IS SPI Undervoltage Shutdown Supply current Device used in SPI mode f = 0 kHz, IO = 0 A f = 20kHz, IO = 0 A 2.5 200 2.8 3.1 13 30 Static Condition Dynamic Condition (t < 500ms) (at least down to 2.5V) (*) 4.4 4.7 V V mV V mA mA 4.5 28 40 V V Parameter Test Condition Min. Typ. Max. Unit
(*) For supply voltages down to 2.5V the output stages are in tristate condition and the status flag is set to low. Below 2.5V the device operates in undefined condition
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L9929
Table 6. Electrical Characteristcs (continued) ( Tj = -40 to +150C; VS = 5 to 28V)
Symbol Logic inputs VIH VIL VH II IEN tdt RS |IOU|max ta tb ta/tb |IOUK| |IOUK| t Logic Input Voltage High IN1, IN2, DI, EN Logic Input Voltage Low IN1, IN2, DI, EN Logic Input Voltage Hysteresis IN1, IN2, DI, EN Logic Input Current IN1, IN2, DI Logic Input Current EN Detection Time EN, DI Switch on Resistance LS Switch on Resistance HS Switch-off Current (*) Switch-off time Blanking time Tracking Short circuit detection current (*) Short Circuit Current Trecking (*) Reactivation time after internal shut down Leakage Current Free-wheel diode forward voltage Outputhigh" (SF not set) Outputlow" (SF set) Overcurrent- or overtemperature shut down to reactivation of the output stage Output stage switched off IO = 3A, VS = 0V VSF = 5V VSF = 0.5V VSF = 0.8V VSF = 1V Timing f Maximum PWM Frequency min. operating time 10s Device can not be controlled with higher frequency (specify in max ratings?) f = 1/(ta+tb) IN1 --> OUT1 or IN2 --> OUT2 OUT1H--> OUT1L, OUT2H--> OUT2L, IOUT = 3 A OUT1L--> OUT1H, OUT2L--> OUT2H DI --> OUTn, En --> OUTn VS = on --> output stage active 1 2 30 kHz 350 400 400 ROUT-Vs, VS > 5 V ROUT-GND, VS > 5 V -40 C < Tj < 165 C Tj < 175 C 7.8 12 8 1.3 8.9 1.3 VI 1V VIEN 1V 3 150 150 8.6 2.5 17 11.5 1.5 10.6 2.0 0.1 -200 -125 100 4 250 250 10.5(tbd) 22 15 1.7 200 A A s 2.14 0.86 0.6 V V V A A s m m A A s s Parameter Test Condition Min. Typ. Max. Unit
Power Outputs (OUT1, OUT2)
IL VFD ISF ISF
1 2 20
mA V A A A A
fS tdon tdoff tr tf tddis tdp terr
Switching Frequency during current limitation Output ON-delay Output OFF-delay Output rise time Outout fall time Disable Delay Time Power on Delay Time Delay time for fault detection
20 3 3 1 1 3
50 7.5 5 5 3 7 1 6
kHz s s s s s ms s
(*) In case of SC OUTx to gnd resp. to VS the SC switch off current is always higher than the start value of current regulation (|IOUK| = |IOUK| - |IOUmax|
5/23
L9929
Figure 5. Output delay time
INn 50% 50%
tdon OUTn 90%
tdoff 10%
D01AT472
Figure 6. Disable delay time
DIn 50%
tddis OUTn 10% Z
D01AT473
Figure 7. Output switching time
90% 90%
OUTn
10% tf tr
D01AT474
Figure 8. Current values to be inserted after characterization
LOAD CURRENT
Reaching Switch-off current, limitation phase is started by triggering tb
OVERCURRENT
> typ.10.6 A
typ. 8.6A A CURRENT LIMITATION PHASE
CONTROL SIGNAL
STATUS FLAG
DETAIL A
OVERCURRENT DETECTION ta
typ. 8.6A
tb t a = SWITCH_OFF TIME IN CURRENT LIMITATION t b = CURRENT LIMITATION BLANKING TIME tb
6/23
L9929
Figure 9.
Temperature-depending current-limitation Maximum rating for junction temperature Overtemperature switch-off Switch-off current in case of current limitation For typical 165C < Tj < 175C the maximum current decreases
Imax
for < 1s 175C > typ. 175C typ. 8.6A Tj < typ. 165C
Tolerance range of temperature dependent current reduction Range of Overtemperature switch-off
typ. 8.6A
typ. 2.5A
165C
175C
Tj
Table 5. Electrical Characteristics (continued) Spi Interface The timing of L9929 is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is taken over on the falling edge of the SCK signal. - SS = active without any clocks at SCK is not allowed - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active. Figure 10.
10 9
SS
11
2
1
3
8
SCK
12
4
7
SO
tristate
Bit (n-3)
Bit (n-4)...1
Bit 0; LSB
5
6
SI
MSB IN Bit (n-2) Bit (n-3)
Bit (n-4)...1 LSB IN
n = 16
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L9929
Table 5. Electrical Characteristcs
Symbol Parameter Test Condition Min. Typ. Max. Unit Input SCK (SPI clock input)
VSCKL VSCKH
Low Level High Level Hysteresis Input Capacity Input Current Pull up current source connected to VS L9929 is selected 2 0.1 20 2 0.1
1 0.4 10 50
V V V pF
A
VSCK
CSCK -ISCK
Input SS (Slave select signal)
VSSL VSSH
VSS
Low Level High Level Hysteresis Input Capacity Input Current
1
V V
0.4 10
V pF
A
CSS -ISS
Pull up current source connected to VS
20
50
Input SI (SPI data input)
VSIL VSIH
VSI
Low Level High Level Hysteresis Input Capacity Input Current Guaranteed by design Pull up current source connected to VS ISO = 2mA ISO = -2mA Capacity of the pin in tristate In tristate SPI-Mode Status-Flag-Mode SPI-Mode 200 100 150 -10 4.5 2 20 2 0.1
1
V V
0.4 10 50
V pF
A
CSI -ISI
Output SO (Tristate output of the L9929 (SPI output); On active reset (DI) output SO is in tristate.)
VSOL VSOH CSO -ISO Vi Ic
Timing
Low Level High Level Capacity Leakage Current Input Voltage Input Current Cycle-Time (1) Enable Lead Time (2) Enable Lag Time (3) Data Valid CL = 40pF (4) Data Valid CL = 200pF (referred to L9929) Data Setup Time (5) (referred to master) Data Hold Time (6) Disable Time (7) (referred to L9929)
1
V V
10 10
pF
A
Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode)
0.8 10
V V mA ns ns ns
tcyc tlead tlag tv
40 150 50 20 100
ns ns ns ns ns
tsu th tdis
8/23
L9929
Table 5. Electrical Characteristcs (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
tdt tSCKH tSCKL
Transfer Delay (8) (referred to master) Serial clock high time (9) (referred to master) Access time (10) (referred to master) Clock inactive before chipselect becomes valid (11) Clock inactive after chipselect becomes valid (12)
150 50 8.35 200 200 Load on SO 50pF 20
ns ns
s
ns ns ns
trs
TIMING
Rise-, fall time
Diagnostic Threshold (Open Load Detection DMS > 3.1V, EN < 18V and/or DI > 2V)
VOUT1 VOUT2 VOUT1 VOUT2 IOUT2 IOUT1 tD Diagnostic Current Tracking Diagnostic Current Delay Time
Load is available Load is missing DMS > 3.1V, EN < 0.8V EN < 18V and/or DI > 2V IOUT1 / IOUT2 * After disabling the device, the load has to be demagnetized during tD ,to avoid erroneous OL detection
0.8 0.8 1 700 1000 1.4 30 1000 1500 1.5 VS 0.8 1350 2000 1.6 100
V V V V
A A
ms
3
Truth Table
SPI 4) DIA_REG
Table 7. Truth Table
Pos. DI EN IN1 IN2 OUT1 OUT2 SF 3)
1. Forward 2. Reverse 3. Free-wheeling low 4. Free-wheeling high 5. Disable 6. Enable 7. IN1 disconnected 8. IN2 disconnected 9. DI disconnected 10. EN disconnected 11. Current limit. active 12. Undervoltage active1.)
L L L L H X L L Z X L X X X
H H H H X L H H X Z H X X X
H L L H X X Z X X X X X X X
L H L H X X X Z X X X X X X
H L L H Z Z H X Z Z Z Z Z Z
L H L H Z Z X H Z Z Z Z Z Z
H H H H L Z H L L L H L L L See Diagnostics / Encoding of Failures
13. Overtemperature 2.) 14. Overcurrent 2.)
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L9929
1.) 2.) In case of undervoltage tristate and status-flag are reset automatically. Whenever overcurrent or overtemperature is detected, the fault is stored (i.e. status-flag remains low). The tristate conditions and the status-flag 3) are reset via DI or EN. L = Low H = High X = High or Low Z = High impedance (all output stage transistors are switched off in static state. For more inform. see next page ) Overcurrent: IOUT1,2 >10.6 A Overtemperature: Undervoltage: 3.) 4.) Tj VVs-GND >175C <4.5V (at least down to 2.5V)
If Mode Status-Flag" is selected (see chapter "Diagnostic / Status-Flag") If Mode SPI-Diagnosis is selected (see chapter "Diagnostic / SPI-Interface")
Description of the state Z" The state Z" has, depending on the previous operating condition different meaning. 1. dynamical I. e. the inductive load is current carrying and is switched off according to Pos. 5, 6, 9, 10, 11, 12, 13, or 14 of the truth table a.) All output stage transistors are switched off. b.) The current flow is continued via the free wheeling diodes. c.) Free wheeling is detected by a negative voltage-level at OUn. d.) Switch on of the parallel-transistor of the current carrying diode. f.) Free wheeling is finshed, if the voltage-level on OUn is positive again. 2. statical g.) all output-stages switched off. Figure 11.
CURRENT CARRYNG IVS -IGND FREE WHEELING HIGH IMPEDANCE
ILOAD
VOUn VSVS-VDS
Z -VS
Z
D01AT478
10/23
L9929
4
Diagnostic
The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag Diagnosis. The choise of the Diagnosis-Mode is selected by the voltage-level on pin 12 (DMS Diagnosis Mode Selection). DMS = GND DMS = Vcc Status-Flag SPI-Diagnostic
For the connection of pins SI, SO, SS and SCK/SF see Fig. 13 respectively Fig. 14. 4.1 Status-Flag
The Status-Flag showes the condition tristate". At the following fault-cases the output-stages switches in tristate and set the status-flag from high to low. - Short circuit of OUT1 or OUT2 against VS or GND - Short circuit between OUT1 and OUT2 - Overcurrent - Overtemperature - Undervoltage on VS In cause of short circuit or overcurrent, the fault will be stored. The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again and the status-flag is reset to high-level. In cause of overtemperature the fault will be stored. The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again and the status-flag is reset to high-level. In cause of undervoltage on VBatt the output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is fallen. If the voltage has risen about the specified value again, the output stage switches on again and the status-flag is reset to high-level. The maximum current which can flow under normal operating conditions is limited to typical Imax. = 8.6A . When the maximum current value is reached, the output stages are switched tristate for a fixed time. According to the time-constant the current decreases exponentially until the next switch-on occurs. At the end if the fixed time the output stage switches on again and the status-flag is reset to high-level.
5
5.1
SPI-INTERFACE
General Discription
The serial SPI interface establishes a communication link between L9929 and the systems microcontroller. L9929 always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud (200pF). Applying an active slave select signal at SS L9929 is selected by the SPI master. SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave select signal (High) the data output SO goes into tristate.
11/23
L9929
Figure 12.
DMS
SPI Power Supply
SS
SPI Control:
State Machine Clock Counter Control Bits Parity Generator
SI
Shift Register
DIA_REG
5.2
Power Supply of the SPI-Interface
SPI-Logic and I/O-Pins are alternativ supplied from DMS or Vcc internal, depending on which voltage is higher. That is why diagnosis of the EN-/DI-Pins is always possible, even in case of missing H-Bridge-power supply e.g. during Vorlauf/Nauchlauf". 5.3 1) Characteristics of the SPI Interface When DMS is > 3.1V, the SPI is active, independent of the state of EN or DI and the voltage on VS. During active reset conditions (DMS < 2.5V) the SPI is driven into its default state. When reset becomes inactive, the state machine enters into a waitstate for the next instruction. If the slave select signal at SS is inactive (high), the state machine is forced to enter the waitstate, i.e. the state machine waits for the following instruction. During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the data according to the instruction ( i.e. modification of internal registers) will be triggered by the rising edge of the SS signal. (-> See Note) Chipaddress: In order to establish the option of extended addressing the uppermost two bits of the instruction-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress. To avoid a busconflict the output SO must stay high impedant during the addressing phase of a frame (i.e. until the addressbits are recognised as valid chipaddress). This tristate behavior should be realised in any case, regardless wether the extended addressoption is used or not. If the chipaddress does not match, the according access will be ignored and SO remains high impedant for the complete frame regardless which frametype is applied. Check byte: Simultaneously to the receipt of an SPI instruction L9929 transmitts a check byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bitpattern and a flag indicating an invalid instruction of the previous access.
2) 3)
4)
5)
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L9929
6) 7) On the read access the databits at the SPI input SI are rejected. Invalid instruction/access: An instruction is invalid, if one of the following conditions is fulfilled: - An unused instruction code is detected (see tables with SPI instructions). - In case the previous transmission is not completed in terms of internal data processing. ( Violation of the minimum Access-Time. ) - In case of the previous transmission has detected more than 16 SCK pulses - Reset has occurred (Undervoltage on DMS) If an invalid instruction is detected, any modifications on registers of L9929 are not allowed. In case an unused instruction code occured the databyte "ffh ex" will be transmitted after having sent the check byte. In addition any access is invalid if the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses (-> See Note). 5.4 SPI Communication
Figure 13. Reading access / 8 bit
SS
SI
SPI INSTRUCTION MSB
XXXX XXXX
SO
VERIFICATION BYTE MSB
DATA/8 BIT MSB
D01AT480
5.5
SPI Instruction
The uppermost 2 bit of the instruction byte contains the chipadress. The chipaddress of L9929 is 00.
MSB
7 0
6 0
5 INSTR5
4 INSTR4
3 INSTR3
2 INSTR2
1 INSR1
0 INSR0
Encoding SPI Instruction
bit 7,6 CPAD1,0 00 00 00
bit 5,4,3,2,1,0 INSTR(5...0) 000 000 000 011 001 001 All others Read identifier Read version Read DIA_REG No function
Description
RD_IDENT RD_VERSION RD_DIA
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L9929
5.6 Reset of the Diagnostic Register DIA_REG
On the following conditions DIA_REG is reset: - With the rising edge of the SS-signal after the SPI-Instruction RD_DIA (only if error free while SS, new errors will actualize DIA_REG with the rising edge of SS). - When the voltage on DMS exceeds the threshold for detecting SPI-Mode. (after undervoltage condition or after power up) - - If VS rises over about the undervoltage level, the Bits of DIA_REG are restored (when VS internal or DMS > 3,1V) Verification byte:
MSB
7 Z
Bit
6 Z
Name
5 1
4 0
3 1
2 0
Description
1 1
0 TRANS_F
0 1 2 3 4 5 6 7
TRANS_F
Bit = 1: error detected during previous transfer Bit = 0: previous transfer was recognised as valid Fixed to High Fixed to Low Fixed to High Fixed to Low Fixed to High Send as high impedance Send as high impedance
5.7
Diagnostics/Encoding of Failures (SPI Instructions: RD_DIA)
5 CurrRed 4 CurrLim 3 DIA21 2 DIA20 1 Dia11 0 DIA10
Register: DIA_REG
Description of the SPI Registers
7 Active 6 OT
State of Reset: FFH Access by Controller: Bit Name
Read only
Description
0 1 2 3 4 5 6 7
DIA 10 DIA 11 DIA 20 DIA 21 CurrLim CurrRed OT Active
Diagnosis-Bit1 of OUT1 Diagnosis-Bit2 of OUT1 Diagnosis-Bit1 of OUT2 Diagnosis-Bit2 of OUT2 Is set to 0" in case of current limitation Is set to 0" in case of temperature dependet current limitation Is set to 0" in case of overtemperature Shows the wired-or state of the Pins EN and DI
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L9929
Encoding of the Diagnostic Bits of the Output-Stages OUT1 and OUT2 DIA21 DIA20 DIA11 DIA10
0 0 1 1 0
0 1 0 1 0
0 0 1 1 0
0 1 0 1 0
Short circuit over load (SCOL) Short circuit to battery on OUT1 (SCB1) Short circuit to ground on OUT1 (SCG1) No error detected on OUT1 Open load Short circuit to battery on OUT2 (SCB2) Short circuit to ground on OUT2 (SCG2) No error detected on OUT2 Undervoltage on Pin VS
Description of DIA_REG Bit7
EN DI DIA_REG Bit7
0 0 1 1
0 1 0 1
0 0 1 0
5.8
Device Identifier and Revision Number
The IC's identifier is used for production test purposes and features plug & play functionality depending on the systems software release. It is made up on a device-number and a revision number each one read-only accessible via standardised instructions. The Device number is defined once to allow indentification of different IC-Types by software. The Revision number may be utilised to distinguish different states of hardware. The contents is divided into an upper 4 bit field reserved to define revisions correspondending to specific softwarereleases. The lower 4 bit field is utilised to indentify the actual maskset. Both (SWR and MSR) will start with 0000b and are increased by 1 every time an according modification of the hardware is introduced. 5.9 Reading the IC Identifier (SPI Instruction: RD_IDENT):
IC Identifier1 (Device ID)
7 ID7
Bit
6 ID6
Name
5 ID5
4 ID4
3 ID3
2 ID2
Description
1 ID1
0 ID0
7...0
ID(7...0)
ID-No.: 1010 0001
5.10 Reading the IC revision number (SPI Instruction: RD_VERSION):
IC's revision number
7 SWR3
Bit
6 SWR2
5 SWR1
Name
4 SWR0
3 MSR3
2 MSR2
Description
1 MSR1
0 MSR0
7...4 3...0
SWR(3...0) MSR(3...0)
Revision corresponding to Software release: 0Hex Revision corresponding to Maskset: 8Hex
15/23
L9929
Figure 14. Application example with SPI-Interface
DMS IN1 VOLTAGE REGULATOR VCC IN2 DI C SCK SS SO SI
UB
VBATT
OUT1
POWER-ON RESET
RESET
M
OUT2
I.E. WATCH DOG P
EN
GND
D01AT481
Figure 15. Application example with Status-Flag
47K SF VBATT VOLTAGE REGULATOR VCC IN1 IN2 C DI SS SO SI
DMS
UB
OUT1
POWER-ON RESET
RESET
M
OUT2
I.E. WATCH DOG P
EN
GND
D01AT482
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L9929
Figure 16. Application examples for Overvoltage- and Reverse-Voltage Protection
Version 1 REVERSE POLARITY PROTECTION VIA MAIN RELAIS H-BRIDGE VS VS < 40V
MAIN RELAIS
IGNITION SWITCH
BATTERY
Version 2 REVERSE POLARITY PROTECTION VIA ACTIVE DIODE H-BRIDGE VS VS < 40V
BATTERY
D01AT483
6
ESD-SOLIDITY
The connection pins of the IC have to be protected against Electrostatic Discharge ESD) by suitable integrated protection structures. The integrated circuit has to meet the demand of the Human-Body-Model" with VC = 4kV C = 100pF and R2 = 1,5k (330 for OUT1 and OUT2). Thereby any defect or destruction of the integrated circuit must not occur. The protection structures realized to reach the ESD-strength have to be coordinated. The ESD-strength has to be verified by the test circuit given as below. Figure 17.
S2 R1 (1) (2) S1 US R2
=
V
DCVOLTMETER
C
OUT
S3
D01AT484
For the Pins 4, 5, 6, 7, 14 and 15 UC = + 4kV R1 = 100k R2 = 330 C = 100pF Number of pulses each pin: 18 Frequency: 1Hz Arrangement and performance: The requirements of MIL883D Methode 3015 have to be fulfilled.
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L9929
7
ISO-PULSES
In the main-power-supply-system disturbance transients according to ISO 7637-1 First Edition 1990-06-01 may occur. By means of external components (see Fig. 12) the following maximum ratings of the IC will not be exceeded. statical dynamical for t < 500 ms APPENDIX A
OUT1 OUT2
-1V ...... +40V -2V ...... +40V
Load available Open Load SC -> GND on OUT1 with Load SC -> GND on OUT2 with Load SC -> UB on OUT1 with Load SC -> UB on OUT2 with Load SC -> GND on OUT1 Open Load SC -> GND on OUT2 Open Load SC -> UB on OUT1 Open Load SC -> UB on OUT2 Open Load
1 1 0 0 1 1 0 1 1 1
1 0 0 0 1 1 0 0 0 1 SC detected on normal operation SC detected on normal operation SC detected on normal operation SC detected on normal operation OL not detected Double Fault OL detected OL detected OL not detected Double Fault
Figure 18.
VBatt
int 5V IN1 1.5 mA IN2
OUT1
OUT2
1 mA
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L9929
8
APPENDIX B
Figure 19. Voltage Supply of SPI-Logic and EN/DI-Logic
VBatt
EN DI
EN/DILogic
OutputStage
internal Vcc
DMS
Status EN/DI
DMS = GND EN/DI-Logic is supplied from internal VCC DMS = VCC EN/DI-Logic is supplied from DMS (OR int. VCC)
SO SI SCK SS
SPILogic
Undervoltage on VBatt Failure and Status Output Stage
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L9929
9
Package Information
Figure 20. PowerSO20 Mechanical Data & Package Dimensions
DIM. A a1 a2 a3 b c D (1) D1 (2) E e e3 E1 (1) E2 E3 G H h L N S T 10 0.8 5.8 0 15.5 10.9 0 0.4 0.23 15.8 9.4 13.9 1.27 11.43 11.1 2.9 6.2 0.1 15.9 1.1 1.1 0.031 8(typ.) 8(max. ) 0.394 0.228 0.000 0.610 0.429 0.1 mm MIN. TYP. MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.004 MIN. inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570
Weight: 1.9gr
OUTLINE AND MECHANICAL DATA
(1) "D and E1" do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006") - Critical dimensions: "E", "G" and "a3". (2) For subcontractors, the limit is the one quoted in jedec MO-166
PowerSO20
N
N a2 b e A
R
c DETAIL B a1 E DETAIL A
DETAIL A e3 H
lead
D a3 DETAIL B
20 11
Gage Plane 0.35
slug
-C-
S E2 T E1 BOTTOM VIEW
L
SEATING PLANE G C
(COPLANARITY)
E3
1 1 0
h x 45
PSO20MEC
D1
0056635 I
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L9929
Figure 21. PowerSSO24 Mechanical Data & Package Dimensions
DIM. A A2 a1 b c D
(1)
mm MIN. 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 0.10 0.06 10.10 10.50 0.40 0.55 0.85 0.022 0.398 TYP. MAX. 2.47 2.40 0.075 0.51 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.013 0.009 0.398 0.291
inch TYP. MAX. 0.097 0.094 0.003 0.020 0.012 0.413 0.299 0.031 0.346 0.004 0.002 0.413 0.016 0.033
OUTLINE AND MECHANICAL DATA
E (1) e e3 G G1 H h L N X Y
10 (max) 4.10 6.50 4.70 7.10 0.161 0.256 0.185 0.279
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads. (3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
PowerSSO24
7412828 A
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L9929
10 Revision History
Table 8. Revision History
Date Revision Description of Changes
07-Mar-2005 13-May-2005
1 2
First Issue Add package PowerSSO24
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L9929
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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